Workshop on Fast design of digital systems

The Spain Chapter of the IEEE Circuits and Systems organizes a  Workshop on Fast Design of Digital Systems, which is locally organized by the "Universidad San Pablo CEU" in Madrid, Spain on March 8 and  9, 2018. The workshop is aimed at researchers and hardware engineers and it covers the  fast design of digital systems (e.g. FPGA, ASIC) with the electronic design tool AHIR. AHIR enables the hardware compilation of a circuit description. The input entry is a high‐level programming language and the output is fully functional VHDL.


The workshop will be given by Prof. Madhav P. Desai, from the Indian Institute of Technology, Bombay. There will be both theory (day 1) and lab (day 2) sessions. A coffee will be served at noon. 

 

Location: Escuela Politécnica Superior, Universidad San Pablo CEU. Campus de Montepríncipe ‐ Alcorcón

 

TECHNICAL PROGRAM

 

MARCH 8

 

8:30 – 12:30:     Theoretical session

 

  •  Introduction to the AHIR tool suite
  • Language Aa
  • VHDL generation
  • Verification              

 

MARCH 9

 

8:30 – 12:30:    Lab  session

 

  •  Case study: real‐time ECG characterization

 

BIOGRAPHY OF THE SPEAKER

 

Madhav P. Desai holds a degree in Electrical Engineering from IIT Bombay and a PhD degree from University of Illinois in Urbana‐Champaign. During the period 1992‐1996 he was with the Semiconductor Engineering Group of Digital Equipment Corporation in Hudson, MA, where he worked as Principal Engineer developing two of the fastest CMOS microprocessors in history. Currently, he is a Full Professor at the Department of Electrical Engineering, Indian Institute of Technology, Bombay. His research lines cover VLSI design, circuits and systems, and combinatorial algorithms.

 

More details can be found at https://events.vtools.ieee.org/m/168394