The Spain Chapter of the IEEE Circuits and Systems organized a Workshop on Fast Design of Digital Systems, which was locally organized by the "Universidad San Pablo CEU" in Madrid, Spain on March 8 and 9, 2018. The workshop was held at Escuela Politécnica Superior, University San Pablo CEU in Madrid. It was aimed at researchers and hardware engineers and it covered the fast design of digital systems (e.g. FPGA, ASIC) with the electronic design tool AHIR. AHIR enables the hardware compilation of a circuit description. The input entry is a high‐level programming language and the output is fully functional VHDL.
The workshop was given by Prof. Madhav P. Desai, from the Indian Institute of Technology, Bombay. The first day was devoted to an introduction to the design tool AHIR, and the second day was a lab session. Attendants were engineers, researchers and undergrad students coming from the Spanish Aerospace Institute (INTA), University CEU San Pablo and Universidad Politécnica de Madrid. The attendants were able to develop and debug several algorithms using C as the entry language and obtaining automatically the synthesizable VHDL code.
8:30 – 12:30: Theoretical session
8:30 – 12:30: Lab session
BIOGRAPHY OF THE SPEAKER
Madhav P. Desai holds a degree in Electrical Engineering from IIT Bombay and a PhD degree from University of Illinois in Urbana‐Champaign. During the period 1992‐1996 he was with the Semiconductor Engineering Group of Digital Equipment Corporation in Hudson, MA, where he worked as Principal Engineer developing two of the fastest CMOS microprocessors in history. Currently, he is a Full Professor at the Department of Electrical Engineering, Indian Institute of Technology, Bombay. His research lines cover VLSI design, circuits and systems, and combinatorial algorithms.
More details can be found at https://events.vtools.ieee.org/m/168394